| May 2006 | ||
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| Technical Article: Impact of Lead Contamination on Reliability of Lead Free Alloys (.pdf) | ||
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February 20-22, 2007 |
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Chapter Reports The RTP Chapter membership stands at a healthy 47 members, 18 of those holding CID credentials and 6 of those as CID+. Congratulations to all our members who have shown a commitment to continuing their education and enhancing their professional standing. Our next regular chapter meeting is scheduled for Wednesday, May 17 at the Cisco Systems facility in RTP. The topic is mechanical CAD interfaces using the Intermediate Data Format (IDF). Check our website http://dcchapters.ipc.org/rtp/ for more information. This year, the RTP chapter is pleased to participate in the PCB Design Conference East 2006 scheduled to be held September 25 – 29 at the Marriott Durham Civic Center in Durham, NC. The conference brochure will become available in late spring from UP Media Group at www.pcbeast.com/. Stay on the lookout for more information. Our April meeting was our bi-monthly board meeting on April 12. On May 12, Suzy Webb will be joining us to present her popular class "Designing With your Thumbs". This presentation for layout designers, as well as design engineers, will go through some experience-based 'rules of thumb' for board designing. Suzy will be our mentor for a day and will give us general guidelines for routing, planes, stack up, high speed, EMI and more. You will not want to miss this class! This will be an all-day class held at the Hawthorne Farms Athletic Club in Hillsboro, Oregon. Also, we are holding a special event on May 24 from 4:30 to 7:00pm at UL in Vancouver, WA. UL will be providing a presentation and a tour of their lab. Food and beverages are provided! Thank you, UL! For up-to-date information and to view details for our current and future events, please visit our website at http://dcchapters.ipc.org/pnw. We look forward to serving our members! Report Completed by: Patrick Jabbaz, Xilinx Out last Meeting, took place at Mentor Graphics We started off by having Dan Bowden of Mentor Graphics show us a new tool “IO Designer” It is a tool that allows you to perform pin swaps in FPGA's with ease and it works seamless with Mentor Graphics EDA tools. It allows for pin optimizing at the PCB level, and back annotation at the schematic. The tool has great capabilities and allows for pin optimization of complex IC’s such as FPGAs, something that usually ends up taking an entire day but can now be accomplished in a matter of a few minutes. We then moved onto our main topic. Mark Alexander started off by explaining the issues that are needed to deal with large complex FPGAs, such as parasitics. FPGA Challenge:
Mr. Alexander’s focus was decoupling capacitors, land patterns, placement, quantity, test and measurements. Mr. Alexander then went into more details regarding Decoupling capacitors, placement, values, and quantity. Capacitor placement is dependant on Plane separation of VCC and GND, thin dielectric makes placement less important. Placement within device footprint (backside) it is unnecessary in most cases Good real estate on top surface Peripheral placement is just as good However the fan out of the decoupling cap is most important, in order to reduce inductance. Mark then showed us some sample layouts regarding FPGA and decoupling placement. He then showed us some simulations and power measurements graphs. He then moved on to capacitor quantity. The nominal guideline is 1 capacitor per VCC pin However if decoupling caps are present at the IC package level, then the decoupling network at the PCB level can be relaxed. He then moved on the board stack up and power planes, he showed us a few slides with some good stack-ups examples, also some typical power plane splits that are found on complex PCB designs. Mark then moved on to his last part of the presentation, Measuring PDS impedance. He explained the need to measure and provide at the PCB level means to measure. He showed us the type of connector to place such as mini-SMP coax connectors, they are very small, and can be populated after the board has been assembled. These connectors allows for VNA measurements. He stresses the need for such measurements, especially useful on complex designs. For a copy of the slide presentation please e-mail patrick.jabbaz@xilinx.com
Our next meeting will take place on Tuesday, May 9th 2006 About the Speaker:
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