Chapter Reports

RTP Chapter

The RTP Chapter’s latest meeting was held on January 18 at the Tekelec facility in Morrisville, NC and was attended by 45 designers and engineers. Tekelec provided an excellent catered dinner before our meeting. We were treated to an informative and entertaining presentation by Dr. Bruce Archambeault of IBM titled “EMC and Electromagnetics for the Working Engineer”. Dr. Bruce provided explanations of EMI/EMC and electromagnetics in everyday terms and without the messy mathematics. He also discussed typical mistakes made during PCB design that greatly impact EMI/EMC performance.

Chapter officer elections for 2006 were held and the slate is as follows:

In addition to the chapter officers, the Steering Committee is open to anyone willing to contribute to the success of the chapter. The Steering Committee meets bi-monthly, mostly via conference call. Contact any of the officers listed above for more information. Thanks to all who serve to make the RTP Chapter a continuing success.

This year, the RTP chapter is pleased to participate in the PCB Design Conference East 2006 scheduled to be held September 25 – 29 at the Marriott Durham Civic Center in Durham, NC. The conference brochure will become available in late spring from UP Media Group at http://www.pcbeast.com/.

Report submitted by S. Trasatto, RTP Chapter Secretary
February 15, 2006

Pacific NorthwesT Chapter

This year has been a busy one for the Pacific Northwest Chapter!! Our year was kicked off with our annual meeting - held January 25 at InFocus in Wilsonville. Gil White, of Dynamic Details, presented "Via Fabrication: Blind and Buried, Micro, and Stacked". Gil discussed:

• Definitions of the different types of vias
• Construction and materials
• Design considerations and guidelines
• via-in-pad
• offsets
• snowman
• fabrication process
• cost trade offs

In addition, we had two officers elected to their two-year positions: Gary Kipp is the PNW Chapter’s new president and Barbara Hill maintains her position as Secretary. Pat Grieser has been appointed to fill Gary Kipp’s Vice President position.

Our February executive board meeting was held February 8 at Intel. This meeting was centered around the transitioning roles of the officers and solidifying our educational opportunities for the upcoming year. What a busy year in store!

Our chapter was also fortunate to have a special event on February 15! Ed Dawson, of Peripheral Logic Corporation, along with Chris Wilcox of ADIVA, offered a demo of ADIVA Software. This design evaluation tool seeks and identifies issues for fabrication that are missed in the normal DRC options in CAD layout software. This package improves the designer’s chances of getting into fab more quickly by identifying issues and allowing the corrections to be madeinthe native tool with a few simple key strokes. Our thanks to Dennis Osheim and Peripheral Logic Corporation for hosting this meeting and providing a great lunch and location.

In March, we are offering a special "Back to Basics" seminar on March 10 hosted by Tektronix. Debbie Nygaard of Honeywell, noted PCB designer and trainer,will share the full process from concept to assembly of PC boards.

For up-to-date information and to view details for our current and future events, please visit our website at http://dcchapters.ipc.org/pnw. We look forward to serving our members!

Silicon ValleY Chapter

Report Completed by: Patrick Jabbaz, Xilinx
Time and Date of Meeting: Tuesday Jan 10th, 2006
Meeting minutes (description of the event): How are signals degraded when speeds go up
Speaker: Lee Ritchey
Our last meeting took place at Cadence Design Systems

The presentation started off by having Cadence demonstrate a new feature of Allegro SI 620. We then moved on to Lee’s main presentation.
Lee explained the overall scenario on what happens to signals as speeds goes up, items such as signal loss, jitter, etc. He then went on into details, as to what to do in each type of case, especially in HSD “High Speed Differential”. Lee explained the sources of losses typically found on high speed boards,

1. Dielectric loss in laminate “glass fibers, and resin”
2. Skin effect loss in conductors
   1. basic copper conductivity
   2. Surface roughness
   3. Surface area of conductor

Both losses are frequency sensitive. Lee explained the signal loss is better prevented by the dielectric material we choose, He showed a simulation graph, containing one with signal of different line widths, and another with different laminate materials. The conclusion was that the materials we choose have a greater impact on signal loss than by changing line widths.

The next phase of the presentation covered corrective design practices.
What to do when signal is still too small:

• Select a lower loss material
• Use pre-emphasis to compensate for losses at high frequencies
• Use post emphasis to amplify high frequencies more than low frequencies

The next design question.
How to minimize unwanted parasitics:

• keep PCBs as thin as possible
• Drill the smallest possible holes
• Use back drill where possible for thick boards such as backplanes
• Use laminate with uniform glass weave such as 3313

The conclusions are that we have many engineering decisions available in order to get our high speed signals to meet our requirements.

For a copy of the slide presentation, please email:
patrick.jabbaz@xilinx.com

Our next meeting will take place on Tuesday March 14, 2006
Location:
Mentor Graphics
1001 Ridder Park Drive, San Jose, CA
March 14 Tuesday
Time: 11:30AM - 1:30PM
$1 for members; $5 for non-members
DOOR PRIZE: $25 IPC Publication Certificate

RSVP required > send to SV_IPC@yahoo.com

Title: Power System and I/O Breakout in Complex BGA Designs

Speaker bio: Mark Alexander, Senior Product Application Engineer, Advanced Product Group, Xilinx Inc. Mr. Alexander is involved in the creation of design rules and methodologies for power integrity assurance in large FPGA systems at the die, package and PCB levels. Mr. Alexander has been with Xilinx for seven years, previously worked in areas of PCB design for signal integrity and multi-gigabit transceiver physical media attachment, and holds three patents.